The design of semiconductor integrated circuits and other electrical circuit components involves not only verifying that the circuit functions as intended but that the design also meets any timing requirements for the technology in which the circuits are fabricated.
Static timing analysis is a common method for finding problem areas in an integrated circuit in the design phase. The circuit is simulated to determine if it meets the desired functionality both in terms of logic and timing. A static timing analysis may check a number of different timing requirements for inputs and/or outputs. For example, a setup time requirement is the required time duration that a data signal is required to be available at the input of a cell before a clock signal transition. A hold time requirement is the time duration that a data signal is required to be stable after the clock signal transition.
Generally, static timing analysis can be run for several corner cases, such as high and low temperature, high and low voltages, and best and worst case process conditions. For a “best case process” condition, a particular signal path on the integrated circuit will have a minimum propagation delay. For a “worst case process” condition, the signal path will have a maximum propagation delay.
When a circuit is designed to operate at clock speeds near the edge of what a particular technology can support, it becomes more difficult to meet both the best case process corner and the worst case process corner. For example, if a critical path meets the setup time requirement for a worst case process condition but fails the hold time requirement under a best case process condition, adding a delay to the critical path to correct the hold time violation may cause a violation of the worst case setup time requirement. Meeting timing requirements for both worst case paths and best case paths often results in a comprise by reducing the maximum clock speed and therefore reducing the maximum possible performance at one of the process corners.
Since the designer is not able to predict the actual process conditions for a particular device, the designer must therefore design the device to meet both process corners. In the alternative, individual devices can be screened based on performance after manufacture. Screening is generally used only as an exception and represents an expensive solution.
Since the actual process corners for a particular device are not known during development, prior to fabrication, improved methods and apparatus are desired for meeting timing requirements for both extremities of process conditions.